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19-3504; Rev 2; 2/06
KIT ATION EVALU E AILABL AV
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
General Description
The MAX5073 is a dual-output DC-DC converter with integrated high-side n-channel power MOSFETs. Each output can be configured either as a buck converter or a boost converter. The device is capable of operating from a wide 5.5V to 23V input voltage range. Each output is programmable down to 0.8V in the buck mode and up to 28V in the boost mode with an output voltage accuracy of 1%. In the buck mode, converter 1 and converter 2 can deliver 2A and 1A, respectively. The output switching frequency of each converter can be programmed from 200kHz to 2.2MHz to avoid harmonics in a radio power supply or to reduce the size of the power supply. Each output operates 180 out-of-phase thus reducing input-capacitor ripple current, size, and cost. A SYNC input facilitates external frequency synchronization. Moreover, a CLKOUT output provides out-of-phase clock signal with respect to converter 2, allowing four-phase operation using two MAX5073 ICs in master-slave configuration. The MAX5073 includes an internal digital soft-start that reduces inrush current, eliminates output-voltage overshoot, and ensures monotonic rise in output voltage during power-up. The device includes individual shutdown and a power-good output for each converter. Protection features include output short-circuit protection for buck mode and maximum duty-cycle limit for boost operation, as well as thermal shutdown. The MAX5073 is available in a thermally enhanced 28pin thin QFN package that can dissipate 2.7W at +70C ambient temperature. The device is rated for operation over the -40C to +85C extended, or -40C to +125C automotive temperature range.
Features
4.5V to 5.5V or 5.5V to 23V Input Supply Voltage Range 0.8V (Buck) to 28V (Boost) Output Voltage Two Independent Output DC-DC Converters with Internal Power MOSFETs Each Output can be Configured in Buck or Boost Mode IOUT1 and IOUT2 of 2A and 1A (Respectively) in Buck Mode 180 Out-of-Phase Operation Clock Output for Four Phase Operation Switching Frequency Programmable from 200kHz to 2.2MHz Digital Soft-Start and Sync Input Individual Converter Shutdown and Power-Good Output Short-Circuit Protection (Buck)/Maximum DutyCycle Limit (Boost) Thermal Shutdown Thermally Enhanced 28-Pin Thin QFN Package Dissipates up to 2.7W at +70C
MAX5073
Pin Configuration
BST1/VDD1 PGOOD1 DRAIN1 DRAIN1
EN1
Applications
Automotive Radio Power Supply Point-of-Load DC-DC Converters Telecom Line Card Networking Line Card Power-Over-Ethernet Postregulation for PDs
PGOOD2 SOURCE1 SOURCE1 SGND PGND
21 22 23 24 25 26 27 28 1
CLKOUT
20
19
18
17
16
FB1
TOP VIEW
15 14 13 12
BYPASS VL VL V+ OSC N.C. SYNC
COMP1
Ordering Information
PART MAX5073ETI MAX5073ETI+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE PKG CODE
MAX5073
11 10 9 8
SOURCE2 SOURCE2
28 Thin QFN-EP* T2855-6 (5mm x 5mm) 28 Thin QFN-EP* T2855-6 (5mm x 5mm)
2
BST2/VDD2
3
DRAIN2
4
DRAIN2
5
EN2
6
FB2
7
COMP2
*EP = Exposed pad. +Denotes lead-free package. Ordering Information continued at end of data sheet.
THIN QFN 1
________________________________________________________________ Maxim Integrated Products
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
ABSOLUTE MAXIMUM RATINGS
V+ to PGND............................................................-0.3V to +25V SGND to PGND .....................................................-0.3V to +0.3V VL to SGND...................-0.3V to the lower of +6V or (V+ + 0.3V) BST1/VDD1, BST2/VDD2, DRAIN_, PGOOD2, PGOOD1 to SGND .................................................................-0.3V to +30V BST1/VDD1 to SOURCE1, BST2/VDD2 to SOURCE2 ....................................-0.3V to +6V SOURCE_ to SGND................................................-0.6V to +25V EN_ to SGND .............................................-0.3V to (VL to +0.3V) CLKOUT, BYPASS, OSC, COMP1, COMP2, SYNC, FB_ to SGND ..................-0.3V to (VL + 0.3V) SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms VL, BYPASS to SGND Short Circuit............................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derate 21.3mW/C above +70C).....2758mW* Package Junction-to-Case Thermal Resistance (JC).......2C/W Operating Temperature Ranges: MAX5073ETI (TMIN to TMAX)............................-40C to +85C MAX5073ATI (TMIN to TMAX) .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C *As per JEDEC51 standard.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22F, CVL = 4.7F (ceramic), ROSC = 10k (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER SYSTEM SPECIFICATIONS Input Voltage Range Operating Supply Current V+ IQ (Note 2) VL = V+ VL unloaded, no switching, VFB_ = 1V, V+ = 12V, ROSC = 60k EN_ = 0, PGOOD_ floating, V+ = 12V, ROSC = 60k (MAX5073ETI) EN_ = 0, PGOOD_ floating, V+ = 12V, ROSC = 60k (MAX5073ATI) Efficiency STARTUP/VL REGULATOR VL Undervoltage Lockout Trip Level VL Undervoltage Lockout Hysteresis VL Output Voltage BYPASS OUTPUT BYPASS Voltage BYPASS Load Regulation SOFT-START Digital Ramp Period Soft-Start Steps Internal 6-bit DAC 2048 64 fOSC clock cycles steps VBYPASS VBYPASS IBYPASS = 0, ROSC = 60k (MAX5073ETI) IBYPASS = 0, ROSC = 60k (MAX5073ATI) 0 IBYPASS 50A, ROSC = 60k 1.98 1.975 0 2.00 2.00 2 2.02 2.025 10 V mV VL V+ = 5.5V to 23V, ISOURCE = 0 to 40mA 4.9 UVLO VL falling 3.95 4.1 175 5.2 5.5 4.25 V mV V VOUT1 = 3.3V at 1.5A, VOUT2 = 2.5V at 0.75A (fSW = 1.25MHz) V+ = VL = 5V V+ = 12V V+ = 16V 5.5 4.5 2.2 0.6 0.6 82 80 78 % 23.0 5.5 4 1.2 mA 1.4 V mA SYMBOL CONDITIONS MIN TYP MAX UNITS
V+ Standby Supply Current
ISTBY
2
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22F, CVL = 4.7F (ceramic), ROSC = 10k (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER VOLTAGE-ERROR AMPLIFIER FB_ Input Bias Current FB_ Input Voltage Set Point IB(EA) 0C TA +70C -40C TA +85C -40C TJ +125C (MAX5073ATI only) 0C to +85C FB_ to COMP_ Transconductance INTERNAL PMOSFETS ISWITCH = 100mA, VBST1/VDD1 to VSOURCE1 = 5.2V (MAX5073ETI) ISWITCH = 100mA, VBST1/VDD1 to VSOURCE1 = 5.2V (MAX5073ATI) ISWITCH = 100mA, VBST1/VDD1 to VSOURCE1 = 4.5V (MAX5073ETI) ISWITCH = 100mA, VBST1/VDD1 to VSOURCE1 = 4.5V (MAX5073ATI) ISWITCH = 100mA, VBST2/VDD2 to VSOURCE2 = 5.2V ISWITCH = 100mA, VBST2/VDD2 to VSOURCE2 = 4.5V VOUT1 = 3.3V, V+ = 12V (Note 3) VOUT2 = 2.5V, V+ = 12V (Note 3) EN1 = 0V, VDS = 23V EN2 = 0V, VDS = 23V 195 290 gM -40C to +85C -40C to +125C (MAX5073ATI only) 0.792 0.788 0.788 1.25 1.2 1.2 0.8 0.8 0.8 2 2 2 250 0.808 0.812 0.812 2.70 2.9 2.9 mS V nA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5073
195
330 m
On-Resistance Converter 1
RON1
200
315
200
350
330 350 2 1
630 m 690 A A 10 10 A A
On-Resistance Converter 2
RON2
Minimum Converter 1 Output Current Minimum Converter 2 Output Current Converter 1 MOSFET Leakage Current Converter 2 MOSFET Leakage Current
IOUT1 IOUT2 ILK1 ILK2
INTERNAL SWITCH CURRENT LIMIT Current-Limit Converter 1 Current-Limit Converter 2 ICL1 ICL2 V+ = 12V (MAX5073ETI) V+ = 12V (MAX5073ATI) MAX5073ETI MAX5073ATI 2.3 2.3 1.38 1.38 3 3 1.8 1.8 4.3 4.6 2.10 2.20 A A
_______________________________________________________________________________________
3
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22F, CVL = 4.7F (ceramic), ROSC = 10k (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER INTERNAL OSCILLATOR/SYNC Maximum Duty Cycle Switching Frequency Range Switching Frequency Switching Frequency Accuracy SYNC Frequency Range SYNC High Threshold SYNC Low Threshold SYNC Input Min Pulse Width Clock Output Phase Delay SYNC to SOURCE1 Phase Delay Clock Output High Level Clock Output Low Level EN_ INPUTS EN_ Input High Threshold EN_ Input Low Threshold EN_ Bias Current POWER-GOOD OUTPUT (PGOOD_) PGOOD_ Threshold PGOOD_ Output Voltage PGOOD_ Output Leakage Current THERMAL MANAGEMENT Thermal Shutdown Thermal Hysteresis TSHDN THYST Junction temperature Junction temperature +150 30 C C
PGOODVTH_
SYMBOL
CONDITIONS SYNC = SGND, fSW = 1.25MHz SYNC = SGND, fSW = 2.2MHz Each converter ROSC = 10k, each converter 5.6k ROSC 56k, 1% each converter SYNC input frequency is twice the individual converter frequency
MIN 84 84 200 1125 -15 400 2.4
TYP 86 86 1250
MAX 95 95 2200 1375 +15 4400
UNITS
DMAX fSW fSET
% kHz kHz % kHz V
fSYNC VSYNCH VSYNCL tSYNCIN CLKOUT
PHASE
0.8 100 ROSC = 60k, 1%, with respect to converter 2 / SOURCE2 waveform VL = 5.2V, sourcing 5mA VL = 5.2V, sinking 5mA V+ = VL = 5.2V V+ = VL = 5.2V 2.4 1.8 1.2 0.8 250 PGOOD goes high after VOUT crosses PGOOD_ threshold ISINK = 3mA (MAX5073ETI) ISINK = 3mA (MAX5073ATI) V+ = VL = 5.2V, VPGOOD_ = 23V, VFB_ = 1V 4 0.4 45 45
V ns degrees degrees V V V V nA
SYNCPHASE ROSC = 60k, 1% VCLKOUTH VCLKOUTL VIH VIL IB(EN)
90
92.5
95 0.4 0.52 1
% VOUT V A
VPGOOD_ ILKPGOOD_
Note 1: Specifications at -40C are guaranteed by design and not production tested. Note 2: Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation. Note 3: Output current may be limited by the power dissipation of the package, refer to the Power Dissipation section in the Applications Information.
4
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Typical Operating Characteristics
(V+ = VL = 5.2V, TA = +25C, unless otherwise noted.)
OUTPUT1 EFFICIENCY (BUCK CONVERTER) vs. LOAD CURRENT
MAX5073 toc01
MAX5073
OUTPUT2 EFFICIENCY (BUCK CONVERTER) vs. LOAD CURRENT
MAX5073 toc02
OUTPUT2 EFFICIENCY (BOOST CONVERTER) vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 VIN = 3.3V VIN = 5V
MAX5073 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VOUT = 3.3V fSW = 2.2MHz VIN = 16.0V VIN = 12.0V VIN = 5V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.2 0.3 0.4 0.5 0.6 LOAD (A) 0.7 VOUT = 2.5V fSW = 2.2MHz 0.8 VIN = 16.0V VIN = 12.0V VIN = 5V
100
20 10 0 0.02 0.08 LOAD (A)
VOUT = 12V fSW = 2.2MHz 0.14 0.20
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD (A)
0.9 1.0
OUTPUT1 VOLTAGE (BUCK CONVERTER) vs. LOAD CURRENT
MAX5073 toc04
OUTPUT2 VOLTAGE (BUCK CONVERTER) vs. LOAD CURRENT
MAX5073 toc05
VL OUTPUT VOLTAGE vs. CONVERTER SWITCHING FREQUENCY
5.45 5.40 5.35 VL (V) 5.30 5.25 5.20 VIN = 23V BOTH CONVERTERS SWITCHING
MAX5073 toc06
3.40
2.60
5.50
OUTPUT1 VOLTAGE (V)
OUTPUT2 VOLTGE (V)
3.35
2.55
3.30
2.50
3.25
5.15 5.10 5.05 VIN = 5.5V
3.20 0 0.5 1.0 LOAD (A) 1.5 2.0
2.45 0 0.25 0.50 LOAD (A) 0.75 1.00
5.00 0.1 0.6 1.1 1.6 2.1 2.6 SWITCHING FREQUENCY (fSW) (MHz)
VL DROPOUT VOLTAGE vs. EACH CONVERTER SWITCHING FREQUENCY
MAX5073 toc07
EACH CONVERTER SWITCHING FREQUENCY vs. ROSC
MAX5073 toc08
EACH CONVERTER SWITCHING FREQUENCY vs. TEMPERATURE
SWITCHING FREQUENCY (fSW) (MHz)
MAX5073 toc09
0.35 0.30 DROPOUT VOLTAGE (V) 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1.0 1.5 2.0 VIN = 4.5V VIN = 5.5V
10 SWITCHING FREQUENCY (fSW) (MHz)
10
2.2MHz 1.25MHz 1 0.6MHz 0.3MHz
VIN = 5V
1
0.1 2.5 0 20 40 ROSC (k) 60 80 SWITCHING FREQUENCY (fSW) (MHz)
0.1 -50 0 50 TEMPERATURE (C) 100 150
_______________________________________________________________________________________
5
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25C, unless otherwise noted.)
CONVERTER 1 LOAD-TRANSIENT RESPONSE (BUCK CONVERTER)
MAX5073 toc11
LINE-TRANSIENT RESPONSE (BUCK CONVERTER)
MAX5073 toc10
VIN 5V/div 0V VOUT1 = 3.3V/1.5A AC-COUPLED 200mV/div VOUT2 = 2.5V/0.75A AC-COUPLED 200mV/div 1ms/div 100s/div
VOUT1 = 3.3V AC-COUPLED 200mV/div
IOUT1 1A/div 0A
CONVERTER 2 LOAD-TRANSIENT RESPONSE (BUCK CONVERTER)
MAX5073 toc12
SOFT-START/SOFT-STOP
MAX5073 toc13
VOUT1 = 3.3V AC-COUPLED 100mV/div VOUT2 = 2.5V AC-COUPLED 100mV/div IOUT2 500mA/div 0A
ENABLE 5V/div 0V VOUT1 = 3.3V/1A 2V/div 0V VOUT2 = 2.5V/0.5A 2V/div 0V
100s/div
2ms/div
LOAD-TRANSIENT RESPONSE (BOOST CONVERTER)
MAX5073 toc14
OUT-OF-PHASE OPERATION
MAX5073 toc15
VOUT1 = 3.3V AC-COUPLED 200mV/div VOUT2 = 12V AC-COUPLED 200mV/div
SOURCE2 5V/div 0V SOURCE1 5V/div 0V INPUT RIPPLE AC-COUPLED 20mV/div CLKOUT 5V/div 0V 100ns/div
IOUT2 50mA/div 0A
100s/div
6
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25C, unless otherwise noted.)
MAX5073
EXTERNAL SYNCHRONIZATION
MAX5073 toc16
V+ STANDBY SUPPLY CURRENT (ISTBY) vs. TEMPERATURE
SYNC 5V/div 0V SOURCE1 5V/div 0V VOUT1 RIPPLE AC-COUPLED 20mV/div CLKOUT 5V/div 0V ROSC = 10k 1.4 ISTBY (mA)
MAX5073 toc17
1.8
1.0 ROSC = 60k 0.6
0.2 200ns/div -40 -7 26 59 92 125 TEMPERATURE (C)
V+ SWITCHING SUPPLY CURRENT (ISUPPLY) vs. TEMPERATURE
MAX5073 toc18
OUTPUT1 VOLTAGE (BUCK CONVERTER) vs. TEMPERATURE
3.38 3.36 OUTPUT1 VOLTAGE (V) 3.34 3.32 3.30 3.28 3.26 3.24 3.22 50% LOAD NO LOAD
MAX5073 toc19
35 30 fSW = 2.2MHz ISUPPLY (mA) 25 fSW = 1.25MHz 20 fSW = 600kHz 15 fSW = 300kHz 10 5 -40 -7 26 59 92
3.40
125
3.20 -50 0 50 TEMPERATURE (C) 100 150
TEMPERATURE (C)
OUTPUT2 VOLTAGE (BUCK CONVERTER) vs. TEMPERATURE
MAX5073 toc20
2.60 50% LOAD OUTPUT2 VOLTAGE (V) 2.55 NO LOAD 2.50
2.45
2.40 -50 0 50 TEMPERATURE (C) 100 150
_______________________________________________________________________________________
7
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25C, unless otherwise noted.)
OUTPUT LOAD CURRENT LIMIT vs. TEMPERATURE
2.75 OUTPUT CURRENT LIMIT (A) 2.50 OUTPUT1 2.25 2.00 OUTPUT2 1.75 1.50 1.25 1.00 -40 -5 30 TEMPERATURE (C) 65 100 VIN = 5.5V fSW = 2.2MHz
MAX5073 toc21
FOUR-PHASE OPERATION (SEE FIGURE 3)
MAX5073 toc22
3.00
SOURCE1 (MASTER) 0V SOURCE2 (MASTER) 0V SOURCE1 (SLAVE) 0V SOURCE2 (SLAVE) 400ns/div
Pin Description
PIN 1 NAME CLKOUT FUNCTION Clock Output. CLKOUT is 45 phase-shifted with respect to converter 2 (SOURCE2, Figure 3). Connect CLKOUT (master) to the SYNC of a second MAX5073 (slave) for a four-phase converter.
2
Buck Converter Operation--Bootstrap Flying-Capacitor Connection for Converter 2. Connect BST2/VDD2 to an external ceramic capacitor and diode according to the standard application circuit (Figure 1). BST2/VDD2 Boost Converter Operation--Driver Bypass Capacitor Connection. Connect a low-ESR 0.1F ceramic capacitor from BST2/VDD2 to PGND (Figure 8). Connection to Converter 2 Internal MOSFET Drain. Buck converter operation--use the MOSFET as a high-side switch and connect DRAIN2 to the input supply. Boost converter operation--use the MOSFET as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 8). Active-High Enable Input for Converter 2. Drive EN2 low to shut down converter 2, drive EN2 high for normal operation. Use EN2 in conjunction with EN1 for supply sequencing. Connect to VL for always-on operation. Feedback Input for Converter 2. Connect FB2 to a resistive divider between converter 2's output and SGND to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider from BYPASS to regulator 2's output (Figure 5). See the Setting the Output Voltage section. Compensation Connection for Converter 2. See the Compensation section to compensate converter 2's control loop. External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the switching frequency with the system clock. Each converter frequency is one half the frequency applied to SYNC. Connect SYNC to SGND when not used. No Connection. Not internally connected.
3, 4
DRAIN2
5
EN2
6
FB2
7
COMP2
8 9
SYNC N.C.
8
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Pin Description (continued)
PIN NAME FUNCTION Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (ROSC) to set the switching frequency (see the Oscillator section). Set ROSC for equal to or lower oscillator frequency than the SYNC input frequency when using external synchronization (0.2fSYNC < fOSC < 1.2fSYNC). ROSC is still required when an external clock is connected to the SYNC input. Input Supply Voltage. V+ voltage range from 5.5V to 23V. Connect the V+ and VL together for 4.5V to 5.5V input operation. Bypass with a minimum 0.1F ceramic capacitor to SGND. Internal 5.2V Linear Regulator Output. Use VL to drive the high-side switch at BST1/VDD1 and BST2/VDD2. Bypass VL with a 0.1F capacitor to PGND and a 4.7F ceramic capacitor to SGND. 2.0V Output. Bypass to SGND with a 0.22F or greater ceramic capacitor. Compensation Connection for Converter 1 (See the Compensation Section) Feedback Input for Converter 1. Connect FB1 to a resistive divider between converter 1's output and SGND to program the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive voltagedivider from BYPASS to regulator 1's output (Figure 5). See the Setting the Output Voltage section. Active-High Enable Input for Converter 1. Drive EN1 low to shut down converter 1, drive EN1 high for normal operation. Use EN1 in conjunction with EN2 for supply sequencing. Connect to VL for always-on operation. Connection to the Converter 1 Internal MOSFET Drain. Buck converter operation--use the MOSFET as a high-side switch and connect DRAIN1 to the input supply. Boost converter operation--use the MOSFET as a low-side switch and connect DRAIN1 to the inductor and diode junction.
MAX5073
10
OSC
11 12, 13 14 15 16
V+ VL BYPASS COMP1 FB1
17
EN1
18, 19
DRAIN1
20
Buck Converter Operation--Bootstrap Flying-Capacitor Connection for Converter 1. Connect BST1/VDD1 to an external ceramic capacitor and diode according to the Standard Application Circuit (Figure 1). BST1/VDD1 Boost Converter Operation--Driver Bypass Capacitor Connection. Connect a low-ESR 0.1F ceramic capacitor from BST1/VDD1 to PGND. PGOOD1 PGOOD2 Converter 1 Power-Good Output. Open-drain output goes low when converter 1's output falls below 92.5% of its set regulation voltage. Use PGOOD1, PGOOD2, EN1, and EN2 to sequence the converters. Converter 2 Power-Good Output. Open-drain output goes low when converter 2's output falls below 92.5% of its set regulation voltage. Connection to the Converter 1 Internal MOSFET Source. Buck converter operation--connect SOURCE1 to the switched side of the inductor as shown in Figure 1. Boost converter operation--connect SOURCE1 to PGND. Signal Ground. Connect SGND to the exposed pad. Connect SGND and PGND together at a single point. Power Ground. Connect rectifier diode anode, input capacitor negative, output capacitor negative, and VL bypass capacitor returns to PGND. Connection to the Converter 2 Internal MOSFET Source. Buck converter operation--connect SOURCE2 to the switched side of the inductor as shown in Figure 1. Boost converter operation--connect SOURCE2 to PGND (Figure 8). Exposed Paddle. Connect to SGND. Solder EP to the SGND plane for better thermal performance.
21 22
23, 24 25 26
SOURCE1 SGND PGND
27, 28 EP
SOURCE2 SGND
_______________________________________________________________________________________
9
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
PGOOD2 OUTPUT2 2.5V/1A OUTPUT1 3.3V/2A
VL
CLOCK OUT
28 27 26 25 24 23 22 SOURCE2 PGND SGND SOURCE1 PGOOD2 PGOOD1 21 1 CLKOUT 2 BST2/VDD2
SGND
EP BST1/VDD1 20 DRAIN1 19 DRAIN1 18 MAX5073 EN1 17 FB1 16 COMP1 15 ON OFF
VL
INPUT
3 DRAIN2 4 DRAIN2
ON OFF
INPUT
5 EN2 6 FB2 7 COMP2
SYNC N.C. OSC 8 9 10
SGND VIN = 5.5V TO 23V SYSTEM CLOCK
V+ 11
VL 12
VL BYPASS 13 14
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR THE RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS. PGND SGND
Figure 1. MAX5073 Dual Buck Regulator Application Circuit
Detailed Description
PWM Controller
The MAX5073 converter uses a pulse-width modulation (PWM) voltage-mode control scheme for each out-ofphase controller. It is nonsynchronous rectification and uses an external low-forward-drop Schottky diode for rectification. The controller generates the clock signal by dividing down the internal oscillator or the SYNC input when driven by an external clock, so each controller's switching frequency equals half the oscillator frequency (fSW = fOSC / 2). An internal transconductance error amplifier produces an integrated error voltage at the COMP pin, providing high DC accuracy. The voltage at COMP sets the duty cycle using a PWM comparator and a ramp generator. At each rising edge of the clock, converter 1's high-side n-channel MOSFET turns on and remains on until either the appropriate or maximum duty cycle is reached, or the maximum current limit for the switch is detected. Converter 2 operates out-of-phase, so the second high-side MOSFET turns on at each falling edge of the clock. In the case of buck operation (Figure 1), during each high-side MOSFET's on-time, the associated inductor cur10
rent ramps up. During the second half of the switching cycle, the high-side MOSFET turns off and forward biases the Schottky rectifier. During this time, the SOURCE voltage is clamped to 0.4V (VD) below ground. The inductor releases the stored energy as its current ramps down, and provides current to the output. The bootstrap capacitor is also recharged from the inductance energy when the MOSFET turns off. The circuit goes in discontinuous conduction mode operation at light load, when the inductor current completely discharges before the next cycle commences. Under overload conditions, when the inductor current exceeds the peak current limit of the respective switch, the high-side MOSFET turns off quickly and waits until the next clock cycle. In the case of boost operation, the MOSFET is a lowside switch (Figure 8). During each on-time, the inductor current ramps up. During the second half of the switching cycle, the low-side switch turns off and forward biases the Schottky diode. During this time, the DRAIN voltage is clamped to 0.4V (VD) above VOUT_ and the inductor provides energy to the output as well as replenishes the output capacitor charge.
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Internal Oscillator/Out-of-Phase Operation
The internal oscillator generates the 180 out-of-phase clock signal required by each regulator. The internal oscillator frequency is programmable from 400kHz to 4.4MHz using a single 1% resistor at ROSC. Use the following equation to calculate ROSC: ROSC = 25 x 10 fOSC
9
input of the slave. The effective input ripple switching frequency shall be four times the individual converter's switching frequency. When driving the master converter using external clock at SYNC, set the clock duty cycle to 50% for a 90 phase-shifted operation.
MAX5073
Input Voltage (V+)/Internal Linear Regulator (VL)
All internal control circuitry operates from an internally regulated nominal voltage of 5.2V (VL). At higher input voltages (V+) of 5.5V to 23V, VL is regulated to 5.2V. At 5.5V or below, the internal linear regulator operates in dropout mode, where VL follows V+. Depending on the load on VL, the dropout voltage can be high enough to reduce VL below the undervoltage lockout (UVLO) threshold. For input voltages of less than 5.5V, connect V+ and VL together. The load on VL is proportional to the switching frequency of converter 1 and converter 2. See the Dropout Voltage vs. Switching Frequency graph in the Typical Operating Characteristics. For input voltage ranges higher than 5.5V, use the internal regulator. Bypass V+ to SGND with a low-ESR, 0.1F or greater ceramic capacitor placed close to the MAX5073. Current spikes from VL may disturb internal circuitry powered by VL. Bypass VL with a low-ESR, ceramic 0.1F capacitor to PGND and 4.7F capacitor to SGND.
where fOSC is the internal oscillator frequency in hertz and ROSC in ohms. The two independent regulators in the MAX5073 switch 180 out-of-phase to reduce input filtering requirements, to reduce electromagnetic interference (EMI), and to improve efficiency. This effectively lowers component cost and saves board space, making the MAX5073 ideal for cost-sensitive applications. With dual synchronized out-of-phase operation, the MAX5073's high-side MOSFETs turn on 180 out-ofphase. The instantaneous input current peaks of both regulators do not overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple current rating, allows for fewer or less expensive capacitors, and reduces shielding requirements for EMI. The out-of-phase waveforms in the Typical Operating Characteristics demonstrate synchronized 180 out-of-phase operation.
Undervoltage Lockout/Soft-Start
The MAX5073 includes an undervoltage lockout with hysteresis and a power-on-reset circuit for converter turn-on and monotonic rise of the output voltage. The rising UVLO threshold is internally set to 4.3V with a 175mV hysteresis. Hysteresis at UVLO eliminates "chattering" during startup. When VL drops below UVLO, the internal switches are turned off. Digital soft-start is provided internally to reduce input surge currents and glitches at the input during turn-on. When UVLO is cleared and EN_ is high, digital softstart slowly ramps up the internal reference voltage in 64 steps. The total soft-start period is 2048 switching cycles of the internal oscillator. To calculate the soft-start period, use the following equation: t SS = 2048 fOSC
Synchronization (SYNC)/ Clock Output (CLKOUT)
The main oscillator can be synchronized to the system clock by applying an external clock (fSYNC) at SYNC. The fSYNC frequency must be twice the required operating frequency of an individual converter. Use a TTL logic signal for the external clock with at least a 100ns pulse width. ROSC is still required when using external synchronization. Program the internal oscillator frequency so 0.2f SYNC < f OSC < 1.2f SYNC . The rising edge of fSYNC synchronizes the turn-on edge of the internal MOSFET (see Figure 3). ROSC = 25 x 109 fOSC
where fOSC is the internal oscillator frequency in hertz and ROSC in ohms, fOSC = 2 x fSW. Two MAX5073s can be connected in the master-slave configuration for four ripple-phase operation. The MAX5073 provides a clock output (CLKOUT) that is 45 phase-shifted with respect to the internal switch turn-on edge. Feed the CLKOUT of the master to the SYNC
where fOSC is the internal oscillator frequency in hertz, which is twice the switching frequency of each converter.
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11
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
V+
MAX5073
CONVERTER 1
LDO
VL
VL
DEAD-TIME CONTROL OSCILLATOR FREQUENCY FOLDBACK Q N Q
BST1/VDD1
DRAIN1
BYPASS
SOURCE1
Q VREF fSW / 4 PGOOD1
VREF EN1 DIGITAL SOFT-START FB1 COMP1
0.5VREF
0.92VREF
SYNC CKO OSC
MAIN OSCILLATOR VL
PGOOD2 BST2/VDD2 DRAIN2
OSCILLATOR CONVERTER 2 EN2
VDD2 SOURCE2 FB2 COMP2
Figure 2. Functional Diagram
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
VIN CIN V+ OUTPUT2 DRAIN2 SOURCE2 DRAIN1 SOURCE1 OUTPUT1 OUTPUT4 DRAIN2 SOURCE2 V+ DRAIN1 SOURCE1 OUTPUT3
DUTY CYCLE = 50% CLKIN
SYNC
CLKOUT MASTER
SYNC SLAVE
SYNC
CLKOUT (MASTER)
CLKOUT (SLAVE)
SOURCE1 (MASTER) CLKOUTPHASE SYNCPHASE SOURCE2 (MASTER)
SOURCE1 (SLAVE)
SOURCE2 (SLAVE)
CIN (RIPPLE)
Figure 3. Synchronized Controllers
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13
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
Enable
The MAX5073 dual converter provides separate enable inputs EN1 and EN2 to individually control or sequence the output voltages. These active-high enable inputs are TTL compatible. Pulling EN_ high ramps up the reference slowly, which provides soft-start at the outputs. Forcing the EN_ low externally disables the individual output and generates a PGOOD_ signal. Use EN1, EN2, and PGOOD1 for sequencing (see Figure 4). Connect PGOOD1 to EN2 to make sure converter 1's output is within regulation before converter 2 starts. Add an RC network from VL to EN1 and EN2 to delay the individual converter. A larger RC time constant means a more delayed output. Sequencing reduces input inrush current and possible chattering. Connect the EN_ to VL for always-on operation.
Current Limit
The internal switch current of each converter is sensed using an internal current mirror. Converter 1 and converter 2 have 2A and 1A internal switches. When the peak switch current crosses the current-limit threshold of 3A (typ) and 1.8A (typ) for converter 1 and converter 2, respectively, the on cycle is terminated immediately and the inductor is allowed to discharge. The next cycle resumes at the next clock pulse. In deep overload or short-circuit conditions when the FB voltage drops below 0.4V, the switching frequency is reduced to 1/4 x fSW to provide sufficient time for the inductor to discharge. During overload conditions, if the voltage across the inductor is not high enough to allow for the inductor current to properly discharge, current runaway may occur. Current runaway can destroy the device in spite of internal thermal-overload protection. Reducing the switching frequency during overload conditions prevents current runaway.
PGOOD_
Converter 1 and converter 2 includes a power-good flag, PGOOD1 and PGOOD2, respectively. Since PGOOD is an open-drain output and can sink 3mA while providing the TTL logic-low signal, pull PGOOD to a logic voltage to provide a logic-level output. PGOOD goes low when converter 1's output drops to 92.5% of its nominal regulated voltage. Connect PGOOD to SGND or leave unconnected if not used.
Thermal-Overload Protection
During continuous short circuit or overload at the output, the power dissipation in the IC can exceed its limit. Internal thermal shutdown is provided to avoid irreversible damage to the device. When the die temperature or junction temperature exceeds +150C, an on-chip thermal sensor shuts down the device, forcing the internal switches to turn off, allowing the IC to cool. The thermal sensor turns the part on again after the junction temperature cools by +30C. During thermal shutdown, both regulators shut down, PGOOD_ go low, and soft-start resets.
VIN VL VL
VIN
OUTPUT2
VL DRAIN2 SOURCE2
V+ DRAIN1 SOURCE1
OUTPUT1
OUTPUT2
VL DRAIN2 SOURCE2
V+ DRAIN1 SOURCE1
OUTPUT1
MAX5073 FB2 VL EN2 FB1 R2 EN1 PGOOD1 VL VL C2 EN2 FB2
MAX5073 FB1 R1 EN1 C1 VL
SEQUENCING--OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1.
R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING.
Figure 4. Power-Supply Sequencing Configurations
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Applications Information
Setting the Switching Frequency
The controller generates the clock signal by dividing down the internal oscillator or the SYNC input signal when driven by an external oscillator. The switching frequency equals half the oscillator frequency (fSW = fOSC / 2). The internal oscillator frequency is set by a resistor (ROSC) connected from OSC to SGND. The relationship between fSW and ROSC is: ROSC = 12.5 x 109 fSW where VDROP1 is the total parasitic voltage drops in the inductor discharge path, which includes the forward voltage drop (VD) of the rectifier, the series resistance of the inductor, and the PC board resistance. VDROP2 is the total resistance in the charging path, which includes the on-resistance of the high-side switch, the series resistance of the inductor, and the PC board resistance. Setting the Output Voltage For 0.8V or greater output voltages, connect a voltagedivider from OUT_ to FB_ to SGND (Figure 5). Select RB (FB_ to SGND resistor) to between 1k and 10k. Calculate RA (OUT_ to FB_ resistor) with the following equation: V RA = RB OUT - 1 VFB where VFB_ = 0.8V (see the Electrical Characteristics table) and VOUT_ can range from VFB_ to 28V (boost operation). For output voltages below 0.8V, set the MAX5073 output voltage by connecting a voltage-divider from the output to FB_ to BYPASS (Figure 5). Select RC (FB to BYPASS resistor) higher than a 50k range. Calculate RA with the following equation: V -V OUT RA = RC FB VBYPASS - VFB where VFB = 0.8V, VBYPASS = 2V (see the Electrical Characteristics table), and VOUT_ can range from 0V to VFB_.
MAX5073
where fSW and fOSC are in hertz, and ROSC is in ohms. For example, a 1250kHz switching frequency is set with ROSC = 10k. Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I2R losses are lower at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase. A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by ROSC. This maintains output regulation even with intermittent SYNC signals. When an external synchronization signal is used, ROSC should be set for the oscillator frequency to be lower than or equal to the SYNC rate (fSYNC).
Buck Converter
Effective Input Voltage Range Although the MAX5073 converters can operate from input supplies ranging from 5.5V to 23V, the input voltage range can be effectively limited by the MAX5073 duty-cycle limitations for a given output voltage. The maximum input voltage is limited by the minimum ontime (tON(MIN)): VIN(MAX) VOUT t ON(MIN) x fSW
FB_
LX_ RA
BYPASS RC
FB_ RB RA MAX5073 LX_
where tON(MIN) is 100ns. The minimum input voltage is limited by the maximum duty cycle (DMAX = 0.88):
MAX5073
+ VDROP1 V VIN(MIN) = OUT + VDROP2 - VDROP1 0.88
VOUT_ > 0.8V
VOUT_ < 0.8V
Figure 5. Adjustable Output Voltage
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15
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Inductor Selection Three key inductor parameters must be specified for operation with the MAX5073: inductance value (L), peak inductor current (IL), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential and the peak-to-peak inductor current (IL). Higher IL allows for a lower inductor value while a lower I L requires a higher inductor value. A lower inductor value minimizes size and cost, improves large-signal transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output ripple voltage for the same output capacitor. On the other hand, higher inductance increases efficiency by reducing the ripple current. However, resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels, especially when the inductance is increased without also allowing for larger inductor dimensions. A good compromise is to choose IL equal to 30% of the full load current. To calculate the inductance use the following equation: L= VOUT (VIN - VOUT ) VIN x fSW x IL The input ripple waveform would be unsymmetrical due to the difference in load current and duty cycle between converter 1 and converter 2. The input ripple is comprised of V Q (caused by the capacitor discharge) and VESR (caused by the ESR of the capacitor). A higher load converter dictates the ESR requirement, while the capacitance requirement is a function of the loading mismatch between the two converters. The worst-case mismatch is when one converter is at full load while the other is at no load or in shutdown. Use low-ESR ceramic capacitors with high ripple-current capability at the input. Assume the contribution from the ESR and capacitor discharge equal to 50%. Calculate the input capacitance and ESR required for a specified ripple using the following equations: ESRIN = VESR IL IOUT + 2
MAX5073
where IL = and CIN = where V D = OUT VIN where IOUT is the maximum output current from either converter 1 or converter 2, and D is the duty cycle for that converter. fSW is the frequency of each individual converter. For example, at VIN = 12V, VOUT = 3.3V at I OUT = 2A, and with L = 3.3H, the ESR and input capacitance are calculated for a peak-to-peak input ripple of 100mV or less, yielding an ESR and capacitance value of 20m and 6.8F for 1.25MHz frequency. Use a 100F capacitor at low input voltages to avoid possible undershoot below the undervoltage lockout threshold during power-on and transient loading. IOUT x D(1 - D) VQ x fSW
(VIN - VOUT )
x VOUT
VIN x fSW x L
where VIN and VOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by ROSC (see the Setting the Switching Frequency section). The peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worse at the maximum input voltage. See the Output Capacitor Selection section to verify that the worst-case output ripple is acceptable. The inductor saturating current is also important to avoid runaway current during output overload and continuous short circuit. Select the ISAT to be higher than the maximum peak current limits of 4.5A and 2.2A for converter 1 and converter 2. Input Capacitors The discontinuous input current waveform of the buck converter causes large ripple currents at the input. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple dictate the input capacitance requirement. Increasing the switching frequency or the inductor value lowers the peak to average current ratio, yielding a lower input capacitance requirement. Note that two converters of MAX5073 run 180 out-of-phase, thereby effectively doubling the switching frequency at the input.
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Output Capacitors The allowable output ripple voltage and the maximum deviation of the output voltage during step load currents determines the output capacitance and its ESR. The output ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors, the entire output ripple is contributed by VESR. Use the ESROUT equation to calculate the ESR requirement and choose the capacitor accordingly. If using ceramic capacitors, assume the contribution to the output ripple voltage from the ESR and the capacitor discharge are equal. Calculate the output capacitance and ESR required for a specified ripple using the following equations: ESROUT = VESR IL being powered. When using a ceramic capacitor, assume 80% and 20% contribution from the output capacitance discharge and the ESR drop, respectively. Use the following equations to calculate the required ESR and capacitance value: ESROUT = VESR ISTEP
MAX5073
I x t RESPONSE COUT = STEP VQ where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth.
Boost Converter
The MAX5073 can be configured for step-up conversion since the internal MOSFET can be used as a low-side switch. Use the following equations to calculate the inductor (LMIN), input capacitor (CIN), and output capacitor (COUT) when using the converter in boost operation. Inductor Choose the minimum inductor value so the converter remains in continuous mode operation at minimum output current (IOMIN). LMIN = where V + VD - VIN D= O VO + VD - VDS and IOMIN = 0.25 x IO The VD is the forward voltage drop of the external Schottky diode, D is the duty cycle, and VDS is the voltage drop across the internal switch. Select the inductor with low DC resistance and with a saturation current (ISAT) rating higher than the peak switch current limit of 4.5A and 2.2A of converter 1 and converter 2, respectively. V2IN x D x 2 x fSW x VO x IOMIN
COUT = where
IL 8 x VQ x fSW
VO _ RIPPLE VESR + VQ where IL is the peak-to-peak inductor current as calculated above and fSW is the individual converter's switching frequency. The allowable deviation of the output voltage during fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the step load current until the controller responds with a greater duty cycle. The response time (t RESPONSE) depends on the closed-loop bandwidth of the converter. The high switching frequency of MAX5073 allows for higher closed-loop bandwidth, reducing t RESPONSE and the output capacitance requirement. The resistive drop across the output capacitor ESR and the capacitor discharge causes a voltage droop during a step load. Use a combination of low-ESR tantalum and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output voltage deviation above the tolerable limits of the electronics
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17
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
Input Capacitor The input current for the boost converter is continuous and the RMS ripple current at the input is low. Calculate the capacitor value and ESR of the input capacitor using the following equations. CIN = IL x D 4 x fSW x VQ VESR IL the following equations to calculate the RMS current, DC loss, and switching loss of each converter. The MAX5073 device is available in a thermally enhanced package and can dissipate up to 2.7W at +70C ambient temperature. The total power dissipation in the package must be limited so the junction temperature does not exceed its absolute maximum rating of +150C at maximum ambient temperature. For the buck converter: D IRMS = (I2DC +I2PK +(IDC x IPK )) x MAX 3 PDC = I2RMS x RDS(ON)MAX where IDC = IO - IL 2 IL 2
ESR = where IL =
(VIN - VDS )
xD
L x fSW
where VDS is the total voltage drop across the internal MOSFET plus the voltage drop across the inductor ESR. IL is the peak-to-peak inductor ripple current as calculated above. VQ is the portion of input ripple due to the capacitor discharge and VESR is the contribution due to ESR of the capacitor. Output Capacitor For the boost converter, the output capacitor supplies the load current when the main switch is ON. The required output capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to be low enough to minimize the voltage drop due to the ESR while supporting the load current. Use the following equation to calculate the output capacitor for a specified output ripple tolerance. VESR ESR = IO I x DMAX COUT = O VQ x fSW IO is the load current, VQ is the portion of the ripple due to the capacitor discharge and VESR is the contribution due to the ESR of the capacitor. DMAX is the maximum duty cycle at minimum input voltage. Power Dissipation The MAX5073 includes a high-frequency, low RDS_ON switching MOSFET. At +85C, the RDS_ON of the internal switch for converter 1 and converter 2 are 290m and 630m, respectively. The DC loss is a function of the RMS current in the switch while the switching loss is a function of switching frequency and input voltage. Use
18
IPK = IO +
See the Electrical Characteristics table for the RDS(ON)MAX value. V x I x (t R + t F ) x fSW PSW = INMAX O 4 For the boost converter: D IRMS = (I2DC +I2PK +(IDC x IPK )) x MAX 3 V xI IIN = O O VIN x
IL =
(VIN - VDS ) x D
L x fSW IL 2 IL 2
IDC = IIN -
IPK = IIN +
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
PDC = I RMS x RDS(ON)MAX
2
where VDS is the drop across the internal MOSFET. See the Electrical Characteristics for the RDS(ON)MAX value. V x I x (tR + tF ) x fSW PSW = O IN 4 where tR and tF are rise and fall times of the internal MOSFET. The tR and tF are typically 20ns, and can be measured in the actual application. The supply current in the MAX5073 is dependent on the switching frequency. See the Typical Operating Characteristics to find the supply current of the MAX5073 at a given operating frequency. The power dissipation (PS) in the device due to supply current (IS) is calculated using following equation. PS = VINMAX x ISUPPLY The total power dissipation PT in the device is: PT = PDC1 + PDC2 + PSW1 + PSW2 + PS where PDC1 and PDC2 are DC losses in converter 1 and converter 2, respectively. PSW1 and PSW2 are switching losses in converter 1 and converter 2. Calculate the temperature rise of the die using the following equation: TJ = TC + (PT x JC) where, JC is the junction-to-case thermal impedance of the package equal to +2C/W. Solder the exposed pad of the package to a large copper area to minimize the caseto-ambient thermal impedance. Measure the temperature of the copper area near the device at a worst-case condition of power dissipation and use +2C/W as JC thermal impedance. The case-to-ambient thermal impedance (C-A) is dependent on how well the heat is transferred from the PC board to the ambient. Use a large copper area to keep the PC board temperature low. The C-A is usually in the +20C/W to +40C/W range .
put. The high switching frequency of MAX5073 allows use of ceramic capacitors at the output. Choose all the passive power components that meet the output ripple, component size, and component cost requirements. Choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. Use a simple pole-zero pair (Type II) compensation if the output capacitor ESR zero frequency is below the unity-gain crossover frequency (fC). Type III compensation is necessary when the ESR zero frequency is higher than fC or when compensating for a continuous mode boost converter that has a right-half-plane zero. Use the following procedure 1 to calculate the compensation network components when fZERO,ESR < fC. Buck Converter Compensation Procedure 1 (See Figure 6) 1) Calculate the fZERO,ESR and LC double pole: fZERO, ESR = fLC = 1 2 x ESR x COUT 1
MAX5073
2 x LOUT x COUT
2) Calculate the unity-gain crossover frequency as: f fC = SW 20 If the fZERO,ESR is lower than fC and close to fLC, use a Type II compensation network where RFCF provides a midband zero fmid,zero, and RFCCF provides a high-frequency pole. 3) Calculate modulator gain GM at the crossover frequency.
VOUT R1 gM
Compensation
The MAX5073 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. The flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, use high-ESR aluminum electrolytic capacitors; for component size-sensitive applications, use low-ESR tantalum or ceramic capacitors at the out-
COMP RF CF CCF
R2
VREF
+
Figure 6. Type II Compensation Network 19
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
GM = VIN VOSC x ESR ESR + (2 x fC x LOUT ) x 0.8 VOUT
RI CI gM VREF + COMP R1 VOUT CCF CF
where VOSC is a peak-to-peak ramp amplitude equal to 1V. The transconductance error amplifier gain is: GE / A = gm x RF The total loop gain at fC should be equal to 1 GM x GE / A = 1
RF
R2
Figure 7. Type III Compensation Network
or RF = VOSC (ESR + 2 x fC x L OUT )VOUT 0.8 x VIN x gm x ESR where: CF = 1 2 x 0.75 x fLC x RF
4) Place a zero at or below the LC double pole: CF = 1 2 x RF x fLC
and RF 10k. 4) Calculate CI for a target unity crossover frequency, fC: CI = 2 x fC x LOUT x COUT x VOSC VIN x RF (fP1 = 5) Place a pole RI = 1 2 x RI x CI 1 2 x fZERO, ESR x CI ) at fZERO,ESR.
5) Place a high-frequency pole at fP = 0.5 x fSW. Procedure 2 (see Figure 7) If the output capacitor used is a low-ESR ceramic type, the ESR frequency is usually far away from the targeted unity crossover frequency (fC). In this case, Type III compensation is recommended. Type III compensation provides two-pole zero pairs. The locations of the zero and poles should be such that the phase margin peaks at fC. fC f = P =5 fC The fZ is a good number to get about 60 phase margin at fC. However, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. 1) Select a crossover frequency: fC fSW 20
6) Place a second zero, f Z2 , at 0.2 x f C or at f LC , whichever is lower. R1 = 1 2 x fZ2 x CI (fP2 = 7) Place a second pole the switching frequency. CCF = - RI 1 2 x RF x CCF ) at 1/2
2) Calculate the LC double-pole frequency, fLC: 1 fLC = 2 x LOUT x COUT 3) Place a zero fZ = 1 2 x R F x C F at 0.75 x fLC
CF (2 x 0.5 x fSW x RF x CF ) - 1
20
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
OUTPUT2 PGOOD2 PGOOD1 OUTPUT1 OUTPUT1 3.3V/2A
PGND
SGND
VL OUTPUT2 12V/0.2A
CLOCK OUT
28 27 26 25 24 23 22 SOURCE2 PGND SGND SOURCE1 PGOOD2 PGOOD1 21 1 CLKOUT SGND 2 BST2/VDD2 BST1/VDD1 20 EP 3 DRAIN2 4 DRAIN2
DRAIN1 19 DRAIN1 18 MAX5073 EN1 17 FB1 16 COMP1 15 ON OFF
VL
INPUT
ON OFF
5 EN2 6 FB2 7 COMP2
SYNC N.C. OSC 8 9 10
V+ 11
VL 12
VL BYPASS 13 14
SYSTEM CLOCK INPUT *CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR THE RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 8. Buck-Boost Application
Boost Converter Compensation
The boost converter compensation gets complicated due to the presence of a right-half-plane zero fZERO,RHP. The right-half-plane zero causes a drop in-phase while adding positive (+1) slope to the gain curve. It is important to drop the gain significantly below unity before the RHP frequency. Use the following procedure to calculate the compensation components. 1) Calculate the LC double-pole frequency, FLC, and the right half plane zero frequency. fLC = 1- D 2 x LOUTCOUT (1 - D) R(MIN) 2 x LOUT
2
where: D =1- VIN
VOUT VOUT R(MIN) = IOUT(MAX)
Target the unity-gain crossover frequency for: fC (fZ1 = 2) Place a zero CF = where RF 10k. fZERO, RHP 5
1
fZERO, RHP =
2 x R F x C F 1
) at 0.75 x fLC.
2 x 0.75 x fLC x RF
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21
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
3) Calculate CI for a target crossover frequency, fC:
2 VOSC (1 - D) + C2 LOCO CI = CRF VIN
on the top and bottom side of the PC board. Do not make a direct connection from the exposed pad copper plane to SGND (pin 25) underneath the IC. 2) Isolate the power components and high-current path from the sensitive analog circuitry. 3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. 4) Connect SGND and PGND together close to the IC at the ground terminals of VL and V+ bypass capacitors. Do not connect them together anywhere else. 5) Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PC boards (2oz vs. 1oz) to enhance full-load efficiency.
where C = 2 fC (fP1 = 4) Place a pole RI = ) 2 x RI x CI at fZERO,RHP. 1 2 x fZERO, RHP x CI 1
(fZ2 = 5) Place the second zero R1 = 1
1 2 x R1 x CI - RI 1
) at fLC.
6) Ensure that the feedback connection to COUT is short and direct. 7) Route high-speed switching nodes (BST_/VDD_, SOURCE_) away from the sensitive analog areas (BYPASS, COMP_, and FB_). Use the internal PC board layer for SGND as EMI shields to keep radiated noise away from the IC, feedback dividers, and analog bypass capacitors.
2 x fLC x CI (fP2 =
6) Place the second pole the switching frequency. CCF =
2 x RF x CCF at 1/2
CF (2 x 0.5 x fSW x RF x CF) - 1
Improving Noise Immunity
In applications where the MAX5073 are subject to noisy environments, adjust the controller's compensation to improve the system's noise immunity. In particular, high-frequency noise coupled into the feedback loop causes jittery duty cycles. One solution is to lower the crossover frequency (see the Compensation section).
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is especially true for dual converters where one channel can affect the other. Refer to the MAX5073 EV kit data sheet for a specific layout example. Use a multilayer board whenever possible for better noise immunity. Follow these guidelines for good PC board layout: 1) For SGND, use a large copper plane under the IC and solder it to the exposed paddle. To effectively use this copper area as a heat exchanger between the PC board and ambient, expose this copper area
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2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
Layout Procedure
1) Place the power components first, with ground terminals adjacent (inductor, CIN_, and COUT_). Make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) Group the gate-drive components (bootstrap diodes and capacitors, and VL bypass capacitor) together near the controller IC. 3) Make the DC-DC controller ground connections as follows: a) Create a small-signal ground plane underneath the IC. b) Connect this plane to SGND and use this plane for the ground connection for the reference (BYPASS), enable, compensation components, feedback dividers, and OSC resistor. c) Connect SGND and PGND together near the input bypass capacitors and the IC (this is the only connection between SGND and PGND).
Ordering Information (continued)
PART MAX5073ATI TEMP RANGE -40C to +125C PIN-PACKAGE PKG CODE
Chip Information
TRANSISTOR COUNT: 5994 PROCESS: BiCMOS
28 Thin QFN-EP* T2855-6 (5mm x 5mm) 28 Thin QFN-EP* T2855-6 (5mm x 5mm)
MAX5073ATI+ -40C to +125C
*EP = Exposed pad. +Denotes lead-free package.
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23
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs MAX5073
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
AAAAA
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
1
2
24
______________________________________________________________________________________
QFN THIN.EPS
2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5073
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-2 T1655-3 T1655N-1 T2055-3
D2
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
E2
exceptions
L
A A1 A3 b D E e k L
MIN. NOM. MAX. MIN. NOM. MAX. 0.15
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC.
DOWN BONDS ALLOWED
- 0.25 - 0.25 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 - 0.30 0.40 0.50 16 40 N 20 28 32 ND 4 10 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
** SEE COMMON DIMENSIONS TABLE
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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